EDN

Software engineering firm ‘obfuscates’ Verilog

SANTA CRUZ, Calif. &#151 Not many software products are designed to make things more complicated, but an upcoming Verilog “source code obfuscator” from software engineering firm Semantic Designs does ...
EDN

Startup embeds RTL Verilog in C++ class library

Santa Cruz, Calif. — Promising a low-cost approach to chip design, startup Tenko Technologies Inc. (San Jose, Calif.) is going into beta test with CvSDL, a C++ class library for design and ...
Hackaday

Learning Verilog For FPGAs: The Tools And Building An Adder

Over the last year we’ve had several posts about the Lattice Semiconductor iCEstick which is shown below. The board looks like an overgrown USB stick with no case, but it is really an FPGA development ...

Evolving Hardware Languages In The Age Of AI And LLMs

This is not about replacing Verilog. It’s about evolving the hardware development stack so engineers can operate at the level ...
Design-Reuse

Software engineering firm 'obfuscates' Verilog

SANTA CRUZ, Calif. — Not many software products are designed to make things more complicated, but an upcoming Verilog "source code obfuscator" from software engineering firm Semantic Designs does just ...